Research Assistant

• Organisation: ACES Lab, Rice University
• Duration: May 2013 to July 2013

Employed symmetric placement of logic blocks in the two cores of dual core PUF to obtain a symmetric design. Proposed and implemented Programmable Delay Logic to match the remaining delay skews due to routing assymetries. Evaluated the whole model by collecting results on intra-chip variations and response entropy/stability for different/identical challenges. Also implemented the model on two different Xilinx XUPV5 FPGA chips to evaluate inter-chip variations. Results collected are used for proof-of-concept in the paper submitted to the Design Automation Conference, 2014. Paper accepted on Feb., 2014.